lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Generic Register Interface (contains various adapters)
Common SystemVerilog components
Pipelines the AXI path with FIFOs
RISC-V Debug Support for our PULP RISC-V Cores
open-source Ethenet media access controller for Ariane on Genesys-2
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
SystemVerilog modules and classes commonly used for verification
HW Design Collateral for Caliptra RoT IP
BaseJump STL: A Standard Template Library for SystemVerilog
Simple single-port AXI memory interface